1. Field of the Invention
The present invention relates to a still-image video signal processing circuit for a MUSE decoder.
2. Description of the Prior Art
FIGS. 1A and 1B of the accompanying drawings show a conventional still-image video signal processing circuit for a MUSE decoder. A MUSE signal from an input terminal 1, i.e., an input digital video signal (input digital color video signal) which has been three-dimensionally sub-sampled, is supplied to a noise removing circuit (noise suppressing circuit) 2. A digital video signal (digital color video signal) from which noise has been removed by the noise removing circuit 2 is supplied to a frame memory FM1 which comprises field memories 3, 4 connected in cascade, the frame memory FM1 having a delay time corresponding to one frame (=2 fields). The digital video signal is first delayed for a period of one field by the front field memory 3. The digital video signal from the front field memory 3 is then supplied to the rear field memory 4, by which the digital video signal is further delayed for a period of one field. The digital video signal from the rear field memory 4 is then supplied to a motion correcting circuit 5 in which the digital video signal of the previous frame is displaced by the value of its motion vector based on an interframe motion vector detecting signal transmitted from an encoder.
The digital video signal from the motion correcting circuit 5 is then supplied to a frame memory FM2 which comprises field memories 6, 7 connected in cascade, the frame memory FM2 having a delay time corresponding to one frame. The digital video signal is also supplied to an interframe interpolating circuit 9. The digital video signal is delayed for a period of one field by the front field memory 6. The digital video signal from the front field memory 6 is supplied to the rear field memory 7 and further delayed for a period of one field thereby. The digital video signal from the rear field memory 7 is supplied to a motion correcting circuit 8, and corrected for motion thereby. The digital video signal which is delayed by two frames with respect to the input digital video signal supplied to the input terminal 1 is fed back to the noise removing circuit 2, in which the noise of the input digital video signal is removed (suppressed).
The input digital video signal, from which the noise has been removed, from the noise removing circuit 2 is supplied to the interframe interpolating circuit 9. The interframe interpolating circuit 9 interpolates, between frames, the input digital video signal with the digital video signal, which has been delayed a period of one frame with respect to the input digital video signal, supplied from the motion correcting circuit 5 to the interframe interpolating circuit 9. The digital video signals from the noise removing circuit 2 and the motion correcting circuit 5 are supplied to a moving-image video signal processing circuit.
Of the digital video signal from the interframe interpolating circuit 9, a digital luminance signal of 32.4 Msps (megasamples per second) is supplied to a rate converting circuit 10 by which it is converted in rate into a digital luminance signal of 24.3 Msps. Thereafter, the digital luminance signal is supplied to a field memory 11, and delayed for a period of one field thereby. The digital luminance signal from the field memory 11 is then supplied to a motion correcting circuit 12, and corrected for motion thereby.
The digital luminance signal from the rate converting circuit 10 is supplied to and interpolated between fields by an interfield interpolating circuit 13 with the digital luminance signal which has been supplied from the motion correcting circuit 12 to the interfield interpolating circuit 13 and delayed one field period with respect to the digital luminance signal from the rate converting circuit 10. The interfield interpolating circuit 13 produces a still-image luminance signal of 48.6 Msps and supplies the same to an output terminal 14.
Of the digital video signal from the interframe interpolating circuit 9, a digital chrominance signal (line sequential signal composed of digital red and blue color difference signals) which has been compressed to a 1/4 time is supplied to a TCI decoder 15, and expanded four times in time thereby. Then, the digital chrominance signal is supplied to and delayed one field by a field memory 16.
The digital chrominance signal of 8.1 Msps from the TCI decoder 15 is supplied to and interpolated between fields by an interfield interpolating circuit 17 with the digital chrominance signal which has been supplied from the field memory 16 and delayed one field period with respect to the digital chrominance signal from the TCI decoder 15. The interfield interpolating circuit 17 produces a still-image chrominance signal of 16.2 Msps and supplies the same to an output terminal 18.
The field memory 11 for delaying the digital luminance signal is required to have a storage capacity of about 3 Mbits, and the field memory 16 for delaying the digital chrominance signal is required to have a storage capacity of about 1 Mbits. Actually, the field memory 11 comprises a frame memory having a storage capacity of about 4 Mbits.
The conventional still-image video signal processing circuit employs two frame memories FM1, FM2, i.e., four field memories 3, 4, 6, 7, for removing noise from and interpolating the digital video signal between frames, and also two field memories 11, 16 for interpolating the digital luminance and chrominance signals between fields. Therefore, these memories are required to have a large storage capacity.